Standards/Ethernet PTP/DP83640
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The National Semiconductor DP83640 Precision PHYTER is an ethernet transceiver that integrates certain features useful for the implementation of the IEEE 1588 standard. The three main features are:
- packet time stamping
- synchronised clock generation (PTP_COC and PTP_RATE register)
- event triggering and time stamping with GPIOs
other technical features include:
- IEEE 1588 V1 and V2 support
- Timestamp resolution of 8 ns (Allows sub 10 ns synchronization to master reference)
- Error-free Operation up to 150 meters CAT5 cable
IEEE 1588
Paket Timestamp
TX
Outgoing IEEE 1588 V1 and V2 Event messages are detected automatically and a timestamp is recorded. For the two-step mode an interrupt can be generated when a timestamp is ready to be read by the PHYTER controller. For the one-step mode the transmitter can also be configured to insert the timestamp directly into Sync messages.
RX
Incoming IEEE 1588 V1 and V2 Event messages are detected automatically and a timestamp is recorded. An interrupt is generated an the timestamp can be read by the PHYTER controller. The timestamp can also be integrated into the received packet for easy transmission to the PHYTER controller.
Event
Output Trigger
A trigger signal based on the IEEE 1588 time value can be put out a desired GPIO. The triggers can generate:
- one-time rising or falling edge
- single pulse with a configurable with
- periodic signal
The device supports up to 8 triggers. They can be put out on single GPIOs or be OR'ed together on single GPIOs.
Input Timestamp
The Event Timestamp Unit can monitor up to 8 events of:
- rising edge
- falling edge
- both
assigned to any of the GPIOs. Event timestamps should be adjusted by 35 ns to compensate for internal delays.
MII
PHY address
The PHY address can be configured with 5 pins. The default setting is 00001. With all bits tied to 0 the PHY enters Isolation Mode where it disables parts of the MII interface.
Broadcast mode
The device is configured to accept broadcast messages by setting a register bit (PHY_CR2: BC_WRITE).
Registers
There are 20 fixed registers (0x00 ... 0x13) and 7 pages with 12 registers (0x14 ... 0x1F) each. In the fixed register PAGESEL (address: 0x13) field PAGE_SEL (bits: 2:0) selects the page to access. The pages are:
- Page 0
- Extended Registers
- Page 1
- Test Registers - Reserved
- Page 2
- Link Diagnostics Registers
- Page 3
- Reserved Registers - Reserved
- Page 4
- PTP 1588 Base Registers
- Page 5
- PTP 1588 Configuration Registers
- Page 6
- PTP 1588 Configuration Registers
RS232 access
The baud rate configured in PTP is 19'200.
Base access
action | command |
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enable mii | miim0 y
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read - phy no. - reg. no | rd 0113 01
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write - phy no. - reg. no - data | wr 0113 0004
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Select page
action | command | response |
---|---|---|
Select Page 4 | wr 0113 0004
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Read selected page | rd 0113 01 |
0004
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Init phyter
action | command |
---|---|
Select Page 4 | wr 0113 0004
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Enable Clock | wr 0114 0004
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Select Page 5 | wr 0113 0005
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Configure TX:
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wr 01 16 AEA5
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Time
Set
action | command |
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Select Page 4 | wr 01 13 0004
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Write Clock_time_ns[15:0] to PTP_TDR | wr 0115 0000
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Write Clock_time_ns[31:16] to PTP_TDR | wr 0115 0000
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Write Clock_time_sec[15:0] to PTP_TDR | wr 0115 0000
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Write Clock_time_sec[31:16] to PTP_TDR | wr 0115 0000
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Write to PTP_CTL with the PTP_Load_Clk bit set | wr 0114 0010
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Read
action | command | response |
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Select Page 4 | wr 0113 0004
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Write to PTP_CTL with the PTP_Rd_Clk bit set | TBD
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Read Clock_time_ns[15:0] from PTP_TDR | rd 0115 01 |
4878
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Read Clock_time_ns[31:16] from PTP_TDR | rd 0115 01 |
055D
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Read Clock_time_sec[15:0] from PTP_TDR | rd 0115 01 |
0DFF
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Read Clock_time_sec[31:16] from PTP_TDR | rd 0115 01 |
0000
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Event
Set
action | command |
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Select Page 5 | wr 0113 0005
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Config PTP_EVNT:
"0100_0001_0000_0011" |
wr 0115 4103
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Read
action | command | response |
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Select Page 4 | wr 0113 0004
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Read PTP_ESTS | rd 011E 01 |
00E5 00A5 07A5
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Read PTP_EDATA | rd 011F 01 |
0370 31F9 0557
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