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This special page shows all uploaded files. When filtered by user, only files where that user uploaded the most recent version of the file are shown.

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descDate Name Thumbnail Size User Description Versions
11:16, 27 February 2013Beckhoff FB1130 system.jpg (file)184 KBZas (Beckhoff FB1130 Piggyback and Motherboard)1
11:15, 27 February 2013Beckhoff FB1130 Ref design.ucf (file)21 KBZas (User Constraint File for Reference Design of Beckhoff for FB1130)1
11:15, 27 February 2013Beckhoff FB1130 piggyback.jpg (file)201 KBZas (Beckhoff Piggyback FB1130 Board for EtherCAT Development)1
11:14, 27 February 2013Beckhoff FB1130 motherboard.jpg (file)780 KBZas (Motherboard developed @ HES-SO for Beckhoff Piggyback FB1130 Board)1
16:00, 25 February 2013Actel CoreMP7 schematic.pdf (file)445 KBZas (Schematics file fo the Actel CoreMP7 Development Kit)1
15:57, 25 February 2013Actel CoreMP7.jpg (file)575 KBZas (Actel Development Kit Core MP7)1
15:51, 25 February 2013FPGA Passive EthernetTab schematics.pdf (file)521 KBZas (Schematics of the Passive Ethernet Tab aka. Passive Ethernet Measurement Point)1
15:40, 25 February 2013Passive Measurement Point small.jpg (file)340 KBZas (Passive Ethernet Measurement Point, used and eeveloped during Diplomaworks in Sweden)1
15:31, 25 February 2013GPS Navman Jupiter30.png (file)603 KBZas (GPS receiver Module Jupiter 30)1
08:40, 25 February 2013Xilinx platform cable usb ii.jpg (file)262 KBZas (Official Xilinx Platform USB Programmer)1
16:02, 18 February 2013Update mgc pkginfo.zip (file)519 BZas (Script for let run HDL Designer < 2010 on the HESSO License Server.)1
10:50, 7 February 2013Presentation en UITWiki.pdf (file)1.01 MBZas (Official Presentatino of the UIT Wiki held 24.01.2012)1
10:49, 24 January 2013FPGA Mezza ADC schematic.pdf (file)69 KBZas (HES-SO FPGA-EBS Mezzanine ADC Extention schematic)2
09:49, 22 January 2013ADC Cirrus CS5368.pdf (file)368 KBZas (Datasheet of the Cirrus Logix CS5368 ADC)1
10:10, 15 January 2013PICEBS v1 schematics.pdf (file)93 KBZas (Schematics of the PICEBS V1 Development Board)2
10:07, 15 January 2013PICEBS1 v1 0 doc.pdf (file)216 KBZas (Documentation of the PICEBS V1 Development Board)1
10:00, 15 January 2013PICEBS1 Box.jpg (file)563 KBZas (HESSO PICEBS v1 Development Board in Box)1
10:00, 15 January 2013PICEBS1.jpg (file)787 KBZas (HESSO PICEBS v1 Development Board)1
09:59, 15 January 2013ARMEBS3 v1 3.jpg (file)776 KBZas (HESSO ARMEBS v1.3 Development Board)1
09:17, 15 January 2013RaspberryPiModelB overview.jpg (file)112 KBZas (Schematic Model of the Raspberry Pi)1
10:05, 22 November 2012FPGA PP HEB lcd schematic.pdf (file)271 KBZas (Schematic of the FPGA Parallelport extentions LCD)1
10:05, 22 November 2012FPGA PP HEB lcd.jpg (file)110 KBZas (FPGA Parallelport extention LCD)1
08:53, 7 November 2012FPGA Mezza Audio ADDA.jpg (file)775 KBZas (Low Cost audio AD-DA Mezzanine Board)1
08:52, 7 November 2012FPGA Mezza Highspeed ADDA.jpg (file)476 KBZas (Highspeed AD-DA Mezzanine Board used for projects IGOR and MOLIS)1
09:56, 8 October 2012FPGA PP heb matrix.jpg (file)236 KBZas (FPGA Parallel Port Board HEB_MATRIX)1
13:14, 4 October 2012FPGA PP HEB Matrix schematic.pdf (file)74 KBZas (Schematic of the HEB Matrix Led Parallel board)1
14:11, 1 October 2012SPI master transceiver.png (file)8 KBZas (HDL-Designer Bloc of the SPI Transceiver)1
14:11, 1 October 2012SPI master multi access.png (file)15 KBZas (Simulation of a Multiaccess for the SPI_FIFO bloc)1
14:10, 1 October 2012SPI master FIFO.png (file)13 KBZas (HDL Deisgner Bloc of the SPI_FIFO Master)1
14:09, 1 October 2012SPI timing.png (file)47 KBZas (SPI Timing Diagram)1
14:09, 1 October 2012SPI master slave.png (file)9 KBZas (SPI Master Slave Architecture)1
11:13, 1 October 2012Microsemi logo.gif (file)7 KBZas (Logo of Microsemi)1
11:11, 1 October 2012Microsemi fp4 programmer.jpg (file)608 KBZas (Programmer FlashPro 4 from Microsemi (Former Actel))1
13:42, 14 September 2012FPGARack v1 0 schematics.pdf (file)310 KBZas (Schematic of the FPGA Rack Educational Board v1.0)2
08:31, 14 September 2012FPGARack v1 0.ucf (file)21 KBZas (Pin Contraint File for Board FPGA Rack v1.0.)2
11:38, 13 September 2012FPGA EBS v2 xc3s1200e.ucf (file)5 KBZas (UCF Pin Constrain File for FPGA-EBS Board equipped with the Spartan 3 XC3S1200E Chip)1
11:38, 13 September 2012FPGA EBS v2 xc3s500e.ucf (file)5 KBZas (UCF Pin Constrain File for FPGA-EBS Board equipped with the Spartan 3 XC3S500E Chip)1
16:13, 17 August 2012FPGA Mezza ADC.jpg (file)255 KBZas (Reverted to version as of 14:12, 17 August 2012)4
16:02, 17 August 2012FPGA Mezza Ethernettap.jpg (file)395 KBZas (Mezzanine for FPGA Board. It has 2 Ethernetconnectors and Physicals plus many debug headers.)1
12:07, 8 August 2012FPGA Mezza Ethernettap schematic.pdf (file)259 KBZas (Schematic of the Ethertap Mezzanine extentions for FPGA-EBS and FPGA-Rack)1
12:07, 12 July 2012Digilent xilinx programmer.jpg (file)15 KBZas (Digilent Xilinx Programmer with Impact support)1
12:01, 12 July 2012Digilent logo.png (file)157 KBZas (Digilent Logo)1
11:57, 12 July 2012Digilent logo.gif (file)3 KBZas (Digilent Logo)1
11:32, 27 June 2012FPGA Rack v1 0.jpg (file)249 KBZas (FPGA Rack Development Board with Spartan 6)1
08:57, 21 June 2012Fpgarack impact 2 10.png (file)20 KBZas (FPGA Rack Flash programmation How-to picture 10)1
08:56, 21 June 2012Fpgarack impact 2 9.png (file)19 KBZas (FPGA Rack Flash programmation How-to picture 9)1
08:56, 21 June 2012Fpgarack impact 2 8.png (file)19 KBZas (FPGA Rack Flash programmation How-to picture 8)1
08:55, 21 June 2012Fpgarack impact 2 7.png (file)14 KBZas (FPGA Rack Flash programmation How-to picture 7)1
08:55, 21 June 2012Fpgarack impact 2 6.png (file)18 KBZas (FPGA Rack Flash programmation How-to picture 6)1
08:55, 21 June 2012Fpgarack impact 2 5.png (file)29 KBZas (FPGA Rack Flash programmation How-to picture 5)1

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