Tools/Xilinx ISE/DCM
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In order to divide the clock frequency, a Digital Clock manager (DCM) module can be instantiated.
Instanciation
Saprtan 6
In a Spartan-6 FPGA, the associated module is a DCM_SP
or a DCM_CLKGEN
.
Here a sample code:
library UNISIM; use UNISIM.vcomponents.all; I_DCM: dcm_clkgen generic map ( clkfx_multiply => 3, clkfx_divide => 8, clkin_period => 10.0 ) port map ( rst => '0', freezedcm => '0', clkin => clockIn, clkfx => clock );
UniSim library
Adding the UniSim to the HDS tool can be done with:
unisim = $ISE_HOME/ISE/vhdl/src/unisims
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Tools/Xilinx_ISE/ISE_Libraries
Tools/Xilinx_ISE
Tools/Xilinx_ISE/UCF_Timing_Constraints