Components/IP/Ethernet
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There are 2 [http://isi.hevs.ch/switzerland/robust-electronics.html ISI] [[Standards/Ethernet/IPs|Ethernet IP]] systems: | There are 2 [http://isi.hevs.ch/switzerland/robust-electronics.html ISI] [[Standards/Ethernet/IPs|Ethernet IP]] systems: | ||
| − | * the [[Standards/Ethernet/IPs/UDP FIFO|light core]] with | + | * the [[Standards/Ethernet/IPs/UDP FIFO|light core]] with [[Standards/Ethernet/arp|ARP]] and UDP/IP capabilities |
| − | * the [[Standards/Ethernet/IPs/dissolver|full core]] with additional | + | * the [[Standards/Ethernet/IPs/dissolver|full core]] with additional [http://en.wikipedia.org/wiki/Internet_Control_Message_Protocol ICMP] (for ping) and [http://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol DHCP] support |
Both designs come in 3 blocks: | Both designs come in 3 blocks: | ||
Revision as of 11:51, 13 February 2013
This IP's can be found on the EDA Repository: svn: https://repos.hevs.ch/svn/eda/
There are 2 ISI Ethernet IP systems:
- the light core with ARP and UDP/IP capabilities
- the full core with additional ICMP (for ping) and DHCP support
Both designs come in 3 blocks:
- a MII to dual port RAM interface
- a protocol decoder which retrieves the payload from the complete frame
- the application part where the user places one block for each function (protocol) to implement
