Components/IP/Ethernet
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Both designs come in 3 blocks: | Both designs come in 3 blocks: | ||
| − | * a [[ | + | * a [[Components/IP/Ethernet/MII to RAM|MII to dual port RAM]] interface |
* a protocol decoder which retrieves the payload from the complete frame | * a protocol decoder which retrieves the payload from the complete frame | ||
* the application part where the user places one block for each function (protocol) to implement | * the application part where the user places one block for each function (protocol) to implement | ||
[[Category:Components]] [[Category:Designs]] [[Category:VHDL]] [[Category:IP]] | [[Category:Components]] [[Category:Designs]] [[Category:VHDL]] [[Category:IP]] | ||
Revision as of 14:25, 1 October 2012
There are 2 ISI Ethernet IP systems:
- the light core with only UDP/IP capabilities
- the full core with additional ARP , ICMP (for ping) and DHCP support
Both designs come in 3 blocks:
- a MII to dual port RAM interface
- a protocol decoder which retrieves the payload from the complete frame
- the application part where the user places one block for each function (protocol) to implement
