Hardware/Parallelport/heb microphone

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Revision as of 10:01, 7 June 2017

The board was designed for the SEm VHDL FSM lab.

It has a beeper which can emit a Morse code signal and a microphone for receiving it.

The beeper is driven directly by a digital I/O line. The microphone's output is amplified and connected to an ADC. The amplified signal is also triggered in order to deliver a simple digital input to the FPGA.

Version Photo Schematics Stock
V1.1 HEB-microphone HEB-microphone Schematic PDF 10 fully mounted
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