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Create the page "VHDL" on this wiki!

• Projects/USLO
  ...ucts/silicon-devices/fpga/spartan-6/lx.html Xilinx Spartan-6 LX FPGA]. The VHDL design is analyzed in the chapter [[Projects/USLO#Hardware_Configuration|Ha
  15 KB (2,438 words) - 10:41, 12 December 2016
• Components/IP/NanoBlaze
  The VHDL processor code includes a disassembler VHDL process which translates the current instruction in the form of a string. The corresponding VHDL code is commented out for synthesis via the <code>pragma translate_off</cod
  17 KB (2,338 words) - 07:35, 28 June 2018
• Tools/Xilinx ISE/DCM
  ...or HDL Designer to generate the concatenated file (else further simulation VHDL code is included and will not be accepted at synthesis) unisim = $ISE_HOME/ISE/vhdl/unisim/work
  2 KB (323 words) - 14:22, 10 August 2015
• Hardware/FPGARack4ethernet
  A VHDL test code with the default UCF Files can be found at the EDA SVN Repository * https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack
  5 KB (731 words) - 10:42, 12 December 2016
• Hardware/FPGARackHiRADDAV1
  '''VHDL/SpinalHDL dev & physical tests :'''
  9 KB (1,395 words) - 09:20, 28 March 2018
• Hardware/CubeSat Gumstix/camera connector
  A [http://hamsterworks.co.nz/mediawiki/index.php/OV7670_camera VHDL design example] provides a good understanding of the camera system.
  3 KB (449 words) - 09:00, 9 December 2015
• Tools/SigasiStudio
  <code>Window -> Preferences -> General -> Content Types -> Text -> VHDL Editor -> Add... -> *.vhg -> OK -> OK</code> ...e>Window -> Preferences -> General -> Content Types -> Text -> Lightweight VHDL Editor -> Add... -> *.vhg -> OK -> OK</code>
  325 B (57 words) - 14:46, 2 March 2016
• Tools/Atom
  ; [https://atom.io/packages/aligner-vhdl aligner-vhdl] : VHDL support for aligner
  4 KB (489 words) - 06:02, 18 May 2017
• Projects/CubeSatCom/Meetings
  VHDL toolchain setup done, developement should now progress faster. ** have to generate stimuli in VHDL for client
  13 KB (1,910 words) - 15:30, 21 August 2017
• Hardware/FPGARackHiRADDAPOWERV1
  '''VHDL/SpinalHDL dev & physical tests :'''
  6 KB (937 words) - 17:15, 4 January 2018
• Projects/CubeSatCom/Modulation
  ... test the algorithms and then coded in [https://en.wikipedia.org/wiki/VHDL VHDL].
  7 KB (1,059 words) - 11:27, 18 October 2017
• Projects/CubeSatCom
  * [https://spinalhdl.github.io/SpinalDoc/ SpinalHDL] to generate VHDL code * [[Tools/Mentor_Modelsim|Modelsim]] for VHDL simulation
  2 KB (274 words) - 06:02, 4 March 2019
• Projects/CubeSatCom/ChannelCoding
  The [https://en.wikipedia.org/wiki/VHDL VHDL] code generated by Spinal
  8 KB (1,174 words) - 16:23, 19 March 2018
• Hardware/Parallelport/heb microphone
  The board was designed for the [http://wiki.hevs.ch/fsi/index.php5/SEm SEm] VHDL FSM lab.
  2 KB (298 words) - 13:32, 22 May 2018
• Components/IP/Command decoder
  ...b</code> and <code>command_length</code> have to match the generics of the VHDL entity. [[Category:Components]] [[Category:Designs]] [[Category:VHDL]] [[Category:IP]]
  3 KB (574 words) - 14:45, 17 November 2021
• Languages/Batch
  ...pts described hereafter can be obtained from https://repos.hevs.ch/svn/eda/VHDL/scripts/ : This folder will later contain generated files like the compiled VHDL files for simulation
  1 KB (192 words) - 15:38, 2 August 2018