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• Hardware/Mezzanine/ADC
  The mezzanine board has four 3.5mm jack input connectors. ...df|FPGA ADC Mezza Schematic PDF]] || 8 Channel (4 * Stereo Jack input) ADC Mezzanine Extension. It uses the [[Media:ADC_Cirrus_CS5368.pdf|Cirrus Logic CS5368 AD
  763 B (108 words) - 07:49, 22 January 2013
• Hardware/Mezzanine/Ethertap
  | V1.0 || [[File:FPGA_Mezza_Ethernettap.jpg|200px|Ethernettap Mezzanine]] || [[Media:FPGA_Mezza_Ethernettap_schematic.pdf|FPGA Ethernettap Mezza Sc [[Category:Hardware]][[Category:Mezzanine]]
  1 KB (148 words) - 06:25, 22 February 2013
• Hardware/Mezzanine/high-speed AD-DA
  == High-speed AD/DA mezzanine board == [[File:FPGA_Mezza_Highspeed_ADDA.jpg|200px|Highspeed AD-DA Mezzanine]]
  621 B (81 words) - 14:50, 7 November 2016
• Hardware/Mezzanine/audio AD-DA
  == Audio AD/DA mezzanine board == [[File:FPGA_Mezza_Audio_ADDA.jpg|200px|Audio AD-DA Mezzanine]]
  2 KB (329 words) - 06:51, 7 November 2012
• Hardware/Mezzanine/PWM
  [[Category:Hardware]] [[Category:Mezzanine]] [[Category:HEB]]
  441 B (60 words) - 13:13, 18 January 2018
• Hardware/Mezzanine/Poetic
  This mezzanine was developped for the FPGA Poetic Board during [https://gitlab.hevs.ch/the The mezzanine board has 8 SMA connectors (DAC output), 2 connectors 2x10 pins (ADC input)
  1 KB (152 words) - 12:00, 1 October 2021

Page text matches

• Hardware
  == Mezzanine Boards == * [[Hardware/Mezzanine/Ethertap|EBS Mezza Parallel I/O and Ethernet tap]]
  6 KB (745 words) - 09:23, 6 September 2022
• Hardware/FPGAEBS
  ! Type || FPGA-EBS Full board || FPGA-EBS Student board || FPGA-EBS Mezzanine || Schematic || UCF || Description ...:FPGA_Mezza_v2_1.jpg|115px|FPGA EBS Mezza V2.1]] [[Hardware/Stock_FPGA-EBS#Mezzanine|boards 40-41]] || [[Media:FPGA_EBS_v2_1_schematics.pdf|PDF]] || [[Media:FP
  4 KB (653 words) - 07:25, 10 March 2020

• File:FPGA Mezza ADC schematic.pdf HES-SO FPGA-EBS Mezzanine ADC Extention schematic (70,646 bytes) - 08:49, 24 January 2013

• File:FPGA Mezza v1 0.jpg HES-SO FPGA-EBS Mezzanine v1.0 (1,056 × 1,200 (120,221 bytes)) - 11:48, 8 March 2012

• File:FPGA Mezza ADC.jpg HES-SO FPGA-EBS ADC Mezzanine (1,600 × 1,275 (260,750 bytes)) - 14:13, 17 August 2012

• File:FPGA Mezza v2 1.jpg HES-SO FPGA-EBS Mezzanine Version v2.1 (1,065 × 1,200 (132,169 bytes)) - 12:04, 8 March 2012

• Hardware/FPGARack
  {{WarningBox|content=Mezzanine Pin <code>T8</code> - <code>MEZ_PB19</code> can't be used if a ''XC6SLX100' * 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible
  2 KB (393 words) - 12:08, 5 April 2017
• Hardware/ARMEBS/3
  ** Mezzanine system : * VIDEO mezzanine : controller with SVGA capabilities
  2 KB (229 words) - 12:41, 26 June 2015

• File:FPGA Mezza Ethernettap schematic.pdf Schematic of the Ethertap Mezzanine extentions for FPGA-EBS and FPGA-Rack (264,953 bytes) - 10:07, 8 August 2012

• Hardware/Stock Mez
  '''Our Hardware stock is placed in A201 and A309. If you take some Mezzanine Boards please change the location of the board you took in the appropriate == [[Hardware/Mezzanine/Ethertap|Ethernet Tap]] ==
  4 KB (310 words) - 11:07, 17 October 2019

• File:FPGA Mezza Ethernettap.jpg Mezzanine for FPGA Board. It has 2 Ethernetconnectors and Physicals plus many debug h (2,243 × 1,200 (404,927 bytes)) - 14:02, 17 August 2012

• Hardware/DAC/AD5547
  ...DAC has been used together with 2 [[Hardware/ADC/AD7760|AD7760 ADCs]] on a mezzanine board used for the MOLIS and IGOR projects.
  539 B (86 words) - 07:42, 7 September 2012
• Hardware/ADC/AD7760
  ...een used together with a [[Hardware/DAC/AD5547|AD5547 2-outputs DAC]] on a mezzanine board used for the MOLIS and IGOR projects.
  449 B (71 words) - 07:42, 7 September 2012
• Hardware/Mezzanine/ADC
  The mezzanine board has four 3.5mm jack input connectors. ...df|FPGA ADC Mezza Schematic PDF]] || 8 Channel (4 * Stereo Jack input) ADC Mezzanine Extension. It uses the [[Media:ADC_Cirrus_CS5368.pdf|Cirrus Logic CS5368 AD
  763 B (108 words) - 07:49, 22 January 2013
• Hardware/Mezzanine/Ethertap
  | V1.0 || [[File:FPGA_Mezza_Ethernettap.jpg|200px|Ethernettap Mezzanine]] || [[Media:FPGA_Mezza_Ethernettap_schematic.pdf|FPGA Ethernettap Mezza Sc [[Category:Hardware]][[Category:Mezzanine]]
  1 KB (148 words) - 06:25, 22 February 2013
• Hardware/Mezzanine/high-speed AD-DA
  == High-speed AD/DA mezzanine board == [[File:FPGA_Mezza_Highspeed_ADDA.jpg|200px|Highspeed AD-DA Mezzanine]]
  621 B (81 words) - 14:50, 7 November 2016
• Hardware/Mezzanine/audio AD-DA
  == Audio AD/DA mezzanine board == [[File:FPGA_Mezza_Audio_ADDA.jpg|200px|Audio AD-DA Mezzanine]]
  2 KB (329 words) - 06:51, 7 November 2012

• File:FPGA Mezza Highspeed ADDA.jpg Highspeed AD-DA Mezzanine Board used for projects IGOR and MOLIS (1,301 × 1,600 (487,848 bytes)) - 06:52, 7 November 2012

• File:FPGA Mezza Audio ADDA.jpg Low Cost audio AD-DA Mezzanine Board (1,237 × 1,600 (793,503 bytes)) - 06:53, 7 November 2012

• Inventory
  * [[Hardware/Stock_Mez|Mezzanine]]
  2 KB (266 words) - 08:29, 5 April 2021