HiRel/CanSat/Master FPGA
(→Connections) |
(→Connections) |
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<!-- S1 bottom, Power board --> | <!-- S1 bottom, Power board --> | ||
− | | rowspan=4 | S1 bottom || rowspan=4 | power || | + | | rowspan=4 | S1 bottom || rowspan=4 | power || TxD || J1.1 || 127 |
|- | |- | ||
− | | | + | | RxD || J1.3 || 124 |
|- | |- | ||
| LED 0 || J1.5 || 121 | | LED 0 || J1.5 || 121 | ||
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<!-- S2 bottom , COM board --> | <!-- S2 bottom , COM board --> | ||
− | | rowspan=4 | S2 bottom || rowspan=4 | Computer On Module || | + | | rowspan=4 | S2 bottom || rowspan=4 | Computer On Module || RxD1 || J1.2 || 126 |
|- | |- | ||
− | | | + | | TxD1 || J1.4 || 123 |
|- | |- | ||
− | | | + | | GPIO 168 || J1.6 || 119 |
|- | |- | ||
− | | | + | | GPIO 167 || J1.8 || 117 |
|- | |- | ||
− | <!-- | + | <!-- S3 bottom, Sensor board --> |
+ | | rowspan=4 | S1 bottom || rowspan=4 | sensors || CS_n || J1.1 || 127 | ||
+ | |- | ||
+ | | MOSI || J1.3 || 124 | ||
+ | |- | ||
+ | | MISO || J1.5 || 121 | ||
+ | |- | ||
+ | | SClk || J1.7 || 118 | ||
+ | |- | ||
+ | <!-- S4 bottom , XBee Board --> | ||
+ | | rowspan=4 | S2 bottom || rowspan=4 | XBee radio || RxD || J1.2 || 126 | ||
+ | |- | ||
+ | | TxD1 || J1.4 || 123 | ||
+ | |- | ||
+ | | reset || J1.6 || 119 | ||
+ | |- | ||
+ | | sleep request || J1.8 || 117 | ||
+ | |- | ||
+ | <!-- S1 top, COM board --> | ||
| S1 top || Computer On Module || colspan=3 | audio signals | | S1 top || Computer On Module || colspan=3 | audio signals | ||
|- | |- | ||
− | <!-- | + | <!-- S2 top, Power board --> |
| rowspan=4 | S2 top || rowspan=4 | power || switch 0 || J3.2 || 133 | | rowspan=4 | S2 top || rowspan=4 | power || switch 0 || J3.2 || 133 | ||
|- | |- | ||
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|- | |- | ||
| switch 3 || J3.8 || 141 | | switch 3 || J3.8 || 141 | ||
+ | |- | ||
+ | <!-- S3 top, XBee board --> | ||
+ | | rowspan=4 | S2 top || rowspan=4 | XBee radio || RSSI PWM || J3.1 || 133 | ||
+ | |- | ||
+ | | associate || J3.3 || 137 | ||
+ | |- | ||
+ | | DIO || J3.5 || 139 | ||
+ | |- | ||
+ | | sleep || J3.7 || 141 | ||
+ | |- | ||
+ | <!-- S4 top, sensor board --> | ||
+ | | rowspan=4 | S2 top || rowspan=4 | sensors || int_n || J3.1 || 133 | ||
+ | |- | ||
+ | | cnvt_n || J3.7 || 141 | ||
|- | |- | ||
|} | |} |
Revision as of 15:35, 12 January 2015
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This board will be the master board on the HiRel/CanSat.
System
The design contains a soft-core processor controlling the different slaves of the HiRel/CanSat via peripheral devices attached to it by an AHB-lite bus system.
Connections
The FPGA board connectors consist of 4 dual Pmods, each having 12 pins. The Pmods are connected to the slave boards via the bottom and the top ring.
connector | board | Signal | Pmod pin | FPGA pin |
---|---|---|---|---|
S1 bottom | power | TxD | J1.1 | 127 |
RxD | J1.3 | 124 | ||
LED 0 | J1.5 | 121 | ||
LED 1 | J1.7 | 118 | ||
S2 bottom | Computer On Module | RxD1 | J1.2 | 126 |
TxD1 | J1.4 | 123 | ||
GPIO 168 | J1.6 | 119 | ||
GPIO 167 | J1.8 | 117 | ||
S1 bottom | sensors | CS_n | J1.1 | 127 |
MOSI | J1.3 | 124 | ||
MISO | J1.5 | 121 | ||
SClk | J1.7 | 118 | ||
S2 bottom | XBee radio | RxD | J1.2 | 126 |
TxD1 | J1.4 | 123 | ||
reset | J1.6 | 119 | ||
sleep request | J1.8 | 117 | ||
S1 top | Computer On Module | audio signals | ||
S2 top | power | switch 0 | J3.2 | 133 |
switch 1 | J3.4 | 137 | ||
switch 2 | J3.6 | 139 | ||
switch 3 | J3.8 | 141 | ||
S2 top | XBee radio | RSSI PWM | J3.1 | 133 |
associate | J3.3 | 137 | ||
DIO | J3.5 | 139 | ||
sleep | J3.7 | 141 | ||
S2 top | sensors | int_n | J3.1 | 133 |
cnvt_n | J3.7 | 141 |
FPGA comparisons
The choice of the FPGA was based on a comparison of synthesis results of a simple AHB-Lite system.
Manufacturer | Device | Estimated Frequency | LUTs / CoreCells | Memory | ||
---|---|---|---|---|---|---|
[MHz] | % | Needed | Available | |||
Xilinx | XC6SLX9 | 75.3 | 807 | 13 | 4 | 32 |
Microsemi | AGL60 | 16.4 | 56896 | 3704 | 2 | 4 |
Microsemi | AGL250 |
As it is visible in the table above, the smaller Microsemi Igloo devices are too small for us. Bigger Microsemi Igloo devices however are not easily available and also quite expensive (>80$). On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$). Furthermore we already use them successfully on our FPGArack board.