HiRel/CanSat/Master FPGA
(→Connections) |
(→Connections) |
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|- | |- | ||
<!-- slave 1, power board, bottom --> | <!-- slave 1, power board, bottom --> | ||
− | | rowspan=8 | slave 1:<br />[[HiRel/CanSat/Slave_Power|power supply]] || rowspan=4 | bottom | + | | rowspan=8 | slave 1:<br />[[HiRel/CanSat/Slave_Power|power supply]] || rowspan=4 | bottom |
+ | | TxD || J2.1 || 14 | ||
|- | |- | ||
− | | RxD || J2.3 || 11 | + | | RxD || J2.3 || 11 |
|- | |- | ||
| LED 0 || J2.5 || 8 || out | | LED 0 || J2.5 || 8 || out | ||
Line 37: | Line 38: | ||
|- | |- | ||
<!-- slave 1, power board, top --> | <!-- slave 1, power board, top --> | ||
− | | rowspan=4 | top | + | | rowspan=4 | top |
+ | | switch 0 || J4.1 || 24 || in | ||
|- | |- | ||
| switch 1 || J4.3 || 27 || in | | switch 1 || J4.3 || 27 || in | ||
Line 46: | Line 48: | ||
|- | |- | ||
<!-- slave 2, XBee Board, bottom --> | <!-- slave 2, XBee Board, bottom --> | ||
− | | rowspan=8 | slave 2:<br />[[HiRel/CanSat/Slave_XBee|XBee radio]] || rowspan=4 | bottom | + | | rowspan=8 | slave 2:<br />[[HiRel/CanSat/Slave_XBee|XBee radio]] || rowspan=4 | bottom |
+ | | RxD || J2.2 || 15 | ||
|- | |- | ||
− | | TxD || J2.4 || 12 | + | | TxD || J2.4 || 12 |
|- | |- | ||
| reset || J2.6 || 9 | | reset || J2.6 || 9 | ||
Line 55: | Line 58: | ||
|- | |- | ||
<!-- slave 2, XBee board, top --> | <!-- slave 2, XBee board, top --> | ||
− | | rowspan=4 | top | + | | rowspan=4 | top |
+ | | RSSI PWM || J4.2 || 23 | ||
|- | |- | ||
| associate || J4.4 || 26 | | associate || J4.4 || 26 | ||
|- | |- | ||
− | | DIO || J4.6 || 30 | + | | DIO || J4.6 || 30 |
|- | |- | ||
− | | sleep || J4.8 || 33 | + | | sleep || J4.8 || 33 |
|- | |- | ||
<!-- slave 3, COM board, bottom --> | <!-- slave 3, COM board, bottom --> | ||
− | | rowspan=5 | slave 3:<br />[[HiRel/CanSat/Slave_Gumstix|Computer On Module]] || rowspan=4 | bottom | + | | rowspan=5 | slave 3:<br />[[HiRel/CanSat/Slave_Gumstix|Computer On Module]] || rowspan=4 | bottom |
+ | | RxD1 || J1.1 || 126 15 | ||
|- | |- | ||
− | | TxD1 || J1.3 || 123 | + | | TxD1 || J1.3 || 123 12 |
|- | |- | ||
− | | GPIO 168 || J1.5 || 119 | + | | GPIO 168 || J1.5 || 119 9 |
|- | |- | ||
− | | GPIO 167 || J1.7 || 117 | + | | GPIO 167 || J1.7 || 117 6 |
|- | |- | ||
<!-- slave 3, COM board, top --> | <!-- slave 3, COM board, top --> | ||
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|- | |- | ||
<!-- slave 4, Sensor board, bottom --> | <!-- slave 4, Sensor board, bottom --> | ||
− | | rowspan=6 | slave 4:<br />[[HiRel/CanSat/Slave_Sensors|sensors]] || rowspan=4 | bottom | + | | rowspan=6 | slave 4:<br />[[HiRel/CanSat/Slave_Sensors|sensors]] || rowspan=4 | bottom |
+ | | CS_n || J1.2 || 126 14|| out | ||
|- | |- | ||
− | | MOSI || J1.4 || 123 || out | + | | MOSI || J1.4 || 123 11|| out |
|- | |- | ||
− | | MISO || J1.6 || 119 || in | + | | MISO || J1.6 || 119 8|| in |
|- | |- | ||
− | | SClk || J1.8 || 117 || out | + | | SClk || J1.8 || 117 5|| out |
|- | |- | ||
<!-- slave 4, sensor board, top --> | <!-- slave 4, sensor board, top --> | ||
− | | rowspan=4 | top | + | | rowspan=4 | top |
+ | | int_n || J3.2 || 133 24 | ||
|- | |- | ||
− | | cnvt_n || J3.8 || 141 | + | | || J3.4 || 27 |
+ | |- | ||
+ | | || J3.6 || 32 | ||
+ | |- | ||
+ | | cnvt_n || J3.8 || 141 35 | ||
|} | |} | ||
Revision as of 10:32, 16 January 2015
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This board will be the master board on the HiRel/CanSat.
System
The design contains a soft-core processor controlling the different slaves of the HiRel/CanSat via peripheral devices attached to it by an AHB-lite bus system.
Connections
The FPGA board hosts a 106.25 MHz oscillator and a button which can be used as a reset signal.
Signal | FPGA pin | FPGA dir |
---|---|---|
clock | 16 | in |
reset_n | 2 | in |
The FPGA board connectors consist of 4 dual Pmods, each having 12 pins. The Pmods are connected to the slave boards via the bottom and the top ring.
board | connector | Signal | Pmod pin | FPGA pin | FPGA dir |
---|---|---|---|---|---|
slave 1: power supply |
bottom | TxD | J2.1 | 14 | |
RxD | J2.3 | 11 | |||
LED 0 | J2.5 | 8 | out | ||
LED 1 | J2.7 | 5 | out | ||
top | switch 0 | J4.1 | 24 | in | |
switch 1 | J4.3 | 27 | in | ||
switch 2 | J4.5 | 32 | in | ||
switch 3 | J4.7 | 35 | in | ||
slave 2: XBee radio |
bottom | RxD | J2.2 | 15 | |
TxD | J2.4 | 12 | |||
reset | J2.6 | 9 | |||
sleep request | J2.8 | 6 | |||
top | RSSI PWM | J4.2 | 23 | ||
associate | J4.4 | 26 | |||
DIO | J4.6 | 30 | |||
sleep | J4.8 | 33 | |||
slave 3: Computer On Module |
bottom | RxD1 | J1.1 | 126 15 | |
TxD1 | J1.3 | 123 12 | |||
GPIO 168 | J1.5 | 119 9 | |||
GPIO 167 | J1.7 | 117 6 | |||
top | audio signals | ||||
slave 4: sensors |
bottom | CS_n | J1.2 | 126 14 | out |
MOSI | J1.4 | 123 11 | out | ||
MISO | J1.6 | 119 8 | in | ||
SClk | J1.8 | 117 5 | out | ||
top | int_n | J3.2 | 133 24 | ||
J3.4 | 27 | ||||
J3.6 | 32 | ||||
cnvt_n | J3.8 | 141 35 |
FPGA comparisons
The choice of the FPGA was based on a comparison of synthesis results of a simple AHB-Lite system.
Manufacturer | Device | Estimated Frequency | LUTs / CoreCells | Memory | ||
---|---|---|---|---|---|---|
[MHz] | % | Needed | Available | |||
Xilinx | XC6SLX9 | 75.3 | 807 | 13 | 4 | 32 |
Microsemi | AGL60 | 16.4 | 56896 | 3704 | 2 | 4 |
Microsemi | AGL250 |
As it is visible in the table above, the smaller Microsemi Igloo devices are too small for us. Bigger Microsemi Igloo devices however are not easily available and also quite expensive (>80$). On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$). Furthermore we already use them successfully on our FPGArack board.