|Type||FPGA Rack||Schematic||User constraints file||Description|
|V1.0||FPGA Rack Edison v1.0||FPGA-Rack Edison v1.0 Schematic PDF||TBD||5 Intel Edison Compute Modules and Microsemi AGL1000 FPGA|
The board comprises a controller FPGA and Linux microprocessor systems. It is tailored for low-power, real-time image processing. The board is compatible with the FPGA Rack Backplane for interconnecting different boards.
A short presentation is given on the Institute's website.
The FPGA while programming and running must hold the following bank voltages :
- Bank 0 : 3.3V
- Bank 1 : 3.3V
- Bank 2 : 1.8V (Big Fat Warning! This bank is used to communicate with the Edisons I/Os which operate at 1.8V.)
- Bank 3 : 3.3V
Intel Edison compute modules
The board can host up to 5 Intel Edison compute modules.
The FPGA connects to each compute module individually with:
- a serial port
- a SPI link, tested up to 6 Mbit/s
- an USB FIFO circuit, tested up to 400 Mbit/s
Additionally, the FPGA connects to a general purpose 24-pin connector and to a VME backplane connector. The 24-pin connector is foreseen for interfacing a camera.
The VME connector at the back is compatible with the HEI Backplane Bus, making it compatible with the other HEI VME rack components. The Edison cluster board can thus be used for controlling an instrument built out of these devices.
Connected signals are:
- backplane controls: MCLK, RST, WCLK0, WCLK1
- parallel bus: A7 ÷ A0, D15 ÷ D0, en, wr, ready, freeze, mode
- SPI bus: CLK, MISO, MOSI, CS0, CS1
- I2C bus: SCl, SDa
- UART: RxD, TxD
By default, the PWR header can be leaved open. This header is used as a debug power header for the Edison in slot U1 (which one with the USB console output called Debug). The FPGA present on the board contains by default a minimal circuit which already drives the power pin of the Edison and the FTDI USB-FIFO circuit.
Design & Programmer Tools
You can use the Actel FlashPro4 with the Libero Suite to design your FPGA circuit and program the FPGA.