Ethernet is standardized as IEEE 802.3. It is used for connecting computers to each other via the Web, and it gets more and more used for connecting embedded systems to the Web.
The most known is Internet Protocol version 4 (IPv4), the fourth revision in the development of the Internet Protocol (IP). Internet Protocol Version 6 (IPv6) is designed to succeed IPv4. IPv6 uses a 128-bit address, whereas IPv4 only uses 32 bits.
An Ethernet frame structure is shown next:
|Preamble||Start of frame delimiter||MAC destination||MAC source||Ethertype or length||Payload||Frame Check Sequence (FCS)|
|7 bytes of 1010 1010||1 byte of 1010 1011||6 bytes||6 bytes||2 bytes||46–1500 bytes||4 bytes|
The FCS is a 32 bit CRC.
Frames are separated by an interframe gap of 12 bytes.
The maximal frame length, from the MAC addresses to the FCS is of 1518 bytes (1514 bytes + 4 FCS bytes). The minimal frame length is of 60 bytes + 4 FCS bytes.
Example: ping request
The following data shows the Wireshark display of a ping request frame:
F0 4D A2 33 B7 EF 00 25 64 C2 6F 6A 08 00 45 00 00 3C 31 98 00 00 80 01 CA DA 99 6D 05 E0 99 6D 05 94 08 00 D5 5B 04 00 74 00 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 61 62 63 64 65 66 67 68 69
Wireshark does not display the preamble and the FCS. From the frame we read:
- the destination MAC address
F0 4D A2 33 B7 EF
- the source MAC address
00 25 64 C2 6F 6A
- the Ethertype (IP)
- the payload
45 00 00 3C 31 98 00 00 80 01 CA DA 99 6D 05 E0 99 6D 05 94 08 00 D5 5B 04 00 74 00 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 61 62 63 64 65 66 67 68 69
MII data sequence
A 100BaseT MII has a 4 bit data interface. The bytes are transferred in a sequence of 2 nibbles, with the least significant nibble first.
The MII data sequence for the preceeding ping request will start with the preamble:
55 55 55 55 55 55 55 5D
followed by the MAC addresses:
0F D4 2A 33 7B FE 00 52 46 2C F6 A6 ...
and so on for the rest of the frame which ends with the last data nibbles:
... 86 96
and finish with the FCS:
36 7A AE 28
Multicast and broadcast
For Ethernet, a multicast MAC address has the LSB of the first octet (first bit transmitted) at 1.
The Internet Assigned Number Authority (IANA) has reserved the Organizationally Unique Identifier (OUI)
01:00:5E for mapping IP multicast addresses to MAC addresses.
After these 24 bits, the next MAC address bit is always
0 and the 23 least significant bits (LSBs) are the same as the IP address LSBs.
In IPv4, multicast IP addresses range from
The 4 most significant bits are
E, the 5 next bits are free and the 23 LSBs are the MAC address LSBs.
With this, 25 IP addresses can share the same MAC address.
Bonjour mDNS frames are multicast with MAC address
01:00:5E:00:00:FB and IP address
PTP messages are multicast with MAC address
01:00:5E:00:01:81 and IP address
For Ethernet, the broadcast MAC address is
ARP frames are broadcast.
The Media Independent Interface (MII) has been specified in order to connect digital systems to an Ethernet link via a dedicated physical interface (PHY) circuit. The digital interface uses standard logic level signal whilst the Ethernet lines carry differential signals. Additionally to converting levels, the PHY does some shaping and controlling such as detecting collisions.
The MII provides the following ports:
Before a register access, PHY devices generally require a preamble of 32 ones to be sent by the MAC on the MDIO line. The access consists of 16 control bits, followed by 16 data bits. The control bits consist of 2 start bits, 2 access type bits (read or write), the PHY address (5 bits) and the register address (5 bits).
During a write command, the MAC provides address and data. For a read command, the PHY takes over the bus at the end of the address bits transmission to supply the MAC with the requested register data.
The "Clause 22" MIIM interface specifies 5 PHY-address bits which allows for up to 32 PHY devices attached to a single MDIO data line. Thus a single MAC can control 32 PHYs.
It also specifies 5 register-address bits which allows up to 32 control registers per PHY.
Additionally, some PHY's have an extension scheme of register paging so that more than 32 registers may be accessed.
Information about the standard MIIM registers can be found in the Linux MII interface definition:
The function of the additional registers is left free for the manufacturer to specify and specific PHY circuits can take advantage of this to implement special functions such as Precision Time Protocol (PTP).
The Reduced Media Independent Interface (RMII) standard reduces the number of pins and uses a single clock.
RMII uses a single clock to sample the data lines whilst MII uses a Tx clock to sample the transmitted bits and a Rx clock to sample the received data.
Early Ethernet links showed a data rate of 10 Mbits per second. The signals were run either on coaxial or on twisted pair cables.
Fast Ethernet (100 Mb/s)
Fast Ethernet links show a data rate of 100 Mbits per second. They usually run on twisted pair copper wires. The devices are connected trough switches.
Gigabit Ethernet (1 Gb/s)
There are 2 HEI Ethernet IP systems:
- the light core with only UDP/IP capabilities
- the full core with additional ARP , ICMP (for ping) and DHCP support
Both designs come in 3 blocks:
- a MII to dual port RAM interface
- a protocol decoder which retrieves the payload from the complete frame
- the application part where the user places one block for each function (protocol) to implement
For both designs testbenches are given. They allow to send predefined packets to the Ethernet cores and record and save the packets sent by the Ethernet cores to a human readable text file. The test benches are based on the MII receiver and the MII sender.