Talk:Standards/HEI 'VME' Backplane Bus
From UIT
- VME - Critical : Write error indication to master (latency implications...)
- VME - Critical : Wait cycles... or not ?
- VME - Note : Data parity -> Hamming
- ETH - Note : Ethernet communication TTP or Adele register based
- ETH - Critical : : Fix bug Ethernet (RAM full, CRC error)
- ETH - Note : RAM - FIFO thing