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| | The board is compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEVs_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]]. Some restrictions due to IOs availablity are shown in the following chapter. | | The board is compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEVs_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]]. Some restrictions due to IOs availablity are shown in the following chapter. |
| − |
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| − | = HEVS VME Compatibility =
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| − |
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| − | {| class="wikitable" style="margin: 0 auto; text-align: center;"
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| − | |- style="text-align:left;"
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| − | ! style="width:8px"|
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| − | ! style="width:64px"|Signal
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| − | ! style="width:64px"|Width
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| − | ! style="width:64px"|Driver
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| − | ! style="width:512px ; text-align:left"|Description
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| − | |-
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| − | ! style="background:#c6efce" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''Axx'''</span>
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| − | | style="background:#ffffff" | 8/16 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | Address bus
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| − | |-
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| − | ! style="background:#7ac1ff" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''Dxx'''</span>
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| − | | style="background:#ffffff" | 16/32 bit
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| − | | style="background:#ffffff" | Master/Slave
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| − | | style="background:#ffffff ; text-align:left" | Data bus
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| − | |-
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| − | ! style="background:#ffcc77" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''ECCxx'''</span>
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| − | | style="background:#ffffff" | 6/8 bit
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| − | | style="background:#ffffff" | Master/Slave
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| − | | style="background:#ffffff ; text-align:left" | ECC bits (7 Hamming Bits + 1 Parity Bit)
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| − | |-
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| − | ! style="background:#ff3a3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''MCLK'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | Main bus clock
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| − | |-
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| − | ! style="background:#ff3a3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''RST'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | ReSeT. Allow the master to reset all slaves racks.
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| − | |-
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| − | ! style="background:#ffaaff" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''EN'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | Enables bus transaction.
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| − | |-
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| − | ! style="background:#ffaaff" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''WR'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | WRite operation when set, else read operation.
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| − | |-
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| − | ! style="background:#ffaaff" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''SREADY'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Slave
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| − | | style="background:#ffffff ; text-align:left" | Slave READY. Pulled low by slave when not ready or when ECC error occurs.
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| − | |-
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| − | ! style="background:#ffaaff" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''MFREEZE'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | Master FREEZE. Set by the master for freeze the bus when ECC error occurs.
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| − | |-
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| − | ! style="background:#ffaaff" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''MODE'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | '1' is 64k*32bit slave card and '0' 256*16bit slave card. Used as MSB bit of address.
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| − | |-
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| − | ! style="background:#7fff7a" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''WCLKx'''</span>
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| − | | style="background:#ffffff" | 2 bit
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| − | | style="background:#ffffff" | Undef.
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| − | | style="background:#ffffff ; text-align:left" | Additionnal clock lines.
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| − | |-
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| − | ! style="background:#ffee77" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''IRQxx'''</span>
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| − | | style="background:#ffffff" | 8 bit
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| − | | style="background:#ffffff" | Undef.
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| − | | style="background:#ffffff ; text-align:left" | User-defined interrupt bits.
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| − | |-
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| − | ! style="background:#DA9694" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''UART_TXD'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | UART-Bus transmission line
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| − | |-
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| − | ! style="background:#DA9694" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''UART_RXD'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Slave
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| − | | style="background:#ffffff ; text-align:left" | UART-Bus receiving line
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| − | |-
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| − | ! style="background:#b1a0c7" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''SPI_CLK'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | SPI-Bus clock signal
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| − | |-
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| − | ! style="background:#b1a0c7" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''SPI_MISO'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Slave
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| − | | style="background:#ffffff ; text-align:left" | SPI-Bus Master In Slave Out
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| − | |-
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| − | ! style="background:#b1a0c7" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''SPI_MOSI'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | SPI-Bus Master Out Slave In
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| − | |-
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| − | ! style="background:#b1a0c7" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''SPI_CS0'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | SPI-Bus Chip-Select 0
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| − | |-
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| − | ! style="background:#b1a0c7" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''SPI_CS1'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | SPI-Bus Chip-Select 1
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| − | |-
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| − | ! style="background:#c4bd97" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''I2C_SCL'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Master
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| − | | style="background:#ffffff ; text-align:left" | I2C-Bus clock line
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| − | |-
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| − | ! style="background:#c4bd97" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''I2C_SDA'''</span>
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| − | | style="background:#ffffff" | 1 bit
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| − | | style="background:#ffffff" | Bi-Directionel
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| − | | style="background:#ffffff ; text-align:left" | I2C-Bus data line
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| − | |-
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| − | ! style="background:#3f3f3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''+12V'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | +12V as defined by the VME Standart
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| − | |-
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| − | ! style="background:#3f3f3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''-12V'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | -12V as defined by the VME Standart
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| − | |-
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| − | ! style="background:#3f3f3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''USER_VDD'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | Free definable user voltage
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| − | |-
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| − | ! style="background:#3f3f3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''+5V_F'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | Filtered +5V for all "Clean" consumers
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| − | |-
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| − | ! style="background:#3f3f3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''+5V_N'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | +5V for all "Noisy" consumers
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| − | |-
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| − | ! style="background:#3f3f3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''+3.3V'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | Filtered +3.3V voltage for all "clean" consumers
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| − | |-
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| − | ! style="background:#3f3f3f" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''GND_N'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | Gnd for all "Noisy" Voltages. That means -12V / +12V / User_VDD / +5V_N
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| − | |-
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| − | ! style="background:#cccccc" |
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| − | | style="background:#3f3f3f" | <span style="color:#FFFFFF">'''GND_F'''</span>
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| − | | style="background:#ffffff" | -
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| − | | style="background:#ffffff" | Backplane
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| − | | style="background:#ffffff ; text-align:left" | Ground for all "Clean" Voltages e.g. +5V_F / +3.3V
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| − | |}
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| | | | |
| | = Hardware features = | | = Hardware features = |
The board comprises a controller FPGA and Linux microprocessor systems.
It is tailored for low-power, real-time image processing.
