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  • | 3 || SClk || A4 || rowspan="2" | I2C control
    2 KB (267 words) - 12:40, 9 December 2015
  • * implement I2C and SPI master and slave in SpinalHDL *[ ] define I2C to FPGArack
    13 KB (1,910 words) - 15:30, 21 August 2017
  • Similarly, the FPGA directly transmits the I2C bus to the carrier board [https://www.silabs.com/documents/public/data-shee
    3 KB (458 words) - 17:16, 22 March 2018
  • * transmit I2C lines from the side connector to the MSP The MSP handles the interfacing to the rest of the satellite via the EPS I2C interface.
    4 KB (691 words) - 14:03, 30 May 2018
  • === I2C master and slave === The I2C master and slave share the same implementation, the master having some addi
    20 KB (3,275 words) - 11:38, 27 August 2018
  • | 3, 5 || I2C 1 | 27, 28 || I2C EEPROM
    5 KB (759 words) - 14:15, 16 June 2020
  • ** 4 UART, 2 SPI, 2 I2C ** 2 UART, 2 MSSP (SPI or I2C)
    6 KB (968 words) - 12:01, 7 February 2023

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