Hardware/FPGARack4ethernet
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== USB serial interface == | == USB serial interface == | ||
− | The [http://www.ftdichip.com/Products/ICs/FT232R.htm USB serial interface] | + | The [http://www.ftdichip.com/Products/ICs/FT232R.htm USB serial interface] powers the board |
+ | if jumper <code>JP1</code> is set on the <code>USB_5V</code> side. | ||
+ | |||
+ | It provides a serial port and a JTAG interface. | ||
+ | The serial port is connected directly to the FPGA. | ||
+ | The JTAG interface can be connected to the FPGA programming lines via zero-Ohm resistors. | ||
+ | This programming mode has not been tested yet. | ||
= JTAG connector = | = JTAG connector = |
Revision as of 19:07, 11 January 2016
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This board is a variant of the FPGA rack board, but with 4 Ethernet connectors.
Type | FPGA Rack | Schematic | UCF | Description |
---|---|---|---|---|
V1.0 | ![]() |
FPGA-Rack-Ethernet4 v1.0 Schematic PDF | FPGA-Rack v1.0 UCF Files | There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150 |
The board is compatible with the FPGA Rack Backplane for interconnecting different boards with the help of the HES-SO Backplane Bus and the HES-SO VME IP Core. It holds 4 Ethernet connectors, each connected to an independent KSZ8041NL PHY.
Ethernet
PHY clocks
All 4 PHYs receive the same 25 MHz clock. This clock signal can be sourced from:
- the quartz oscillator closest to the PHYs (
CLK_PHY_25M
) - the FPGA (
CLK_PHY_FPGA
, pin AB13).
The FPGA can generate the PHY clock from
- a 106.25 MHz quartz (
CLK_106_25M
, pin Y13) - the PHY quartz oscillator (
CLK_PHY_25M
, pin AA12) - one of the PHY Rx or Tx clocks (
ETHA_RX_CLK
,ETHA_TX_CLK
,ETHB_RX_CLK
, …)
The last possibility is foreseen to synchronise the clocks of slave Ethernet ports to the one of a master port.
Management Data Input Output (MDIO)
The serial Management Data Input Output (MDIO) interface is connected independently from each PHY to the FPGA.
Serial ports
The FPGA has 3 serial port connections:
- one via an FT232RL RS232 to USB interface
- 2 via a level translator
- the first goes to a flat cable connector
- the second to the JTAG mini connector
USB serial interface
The USB serial interface powers the board
if jumper JP1
is set on the USB_5V
side.
It provides a serial port and a JTAG interface. The serial port is connected directly to the FPGA. The JTAG interface can be connected to the FPGA programming lines via zero-Ohm resistors. This programming mode has not been tested yet.
JTAG connector
The HEI 10-pin JTAG connector provides:
- a 3.3 V power supply
- 4 JTAG signals for FPGA and Flash programmation
- a minimal serial port (Rx and Tx)
- 2 FPGA I/O lines