User contributions
(Latest | Earliest) View (newer 50 | older 50) (20 | 50 | 100 | 250 | 500)
- 12:57, 4 October 2012 (diff | hist) m Hardware/Mezzanine/Ethertap
- 12:56, 4 October 2012 (diff | hist) m Hardware/Mezzanine/Ethertap
- 12:55, 4 October 2012 (diff | hist) m Hardware/Mezzanine/ADC
- 12:54, 4 October 2012 (diff | hist) m Hardware/Mezzanine/ADC (→ADC)
- 12:54, 4 October 2012 (diff | hist) m Hardware/Mezzanine/ADC
- 12:53, 4 October 2012 (diff | hist) m Hardware/Mezzanine/ADC
- 12:53, 4 October 2012 (diff | hist) m Hardware/Mezzanine/ADC
- 12:52, 4 October 2012 (diff | hist) m Hardware/Stock Mez
- 12:51, 4 October 2012 (diff | hist) m Hardware/Stock Mez (→ADC Mezzanine)
- 12:51, 4 October 2012 (diff | hist) m Hardware/Stock Mez
- 12:51, 4 October 2012 (diff | hist) m Hardware/Mezzanine/Ethertap
- 12:50, 4 October 2012 (diff | hist) N Hardware/Mezzanine/Ethertap (Created page with "{{TOC right}} == ADC == 8 Channel Analog to Digital Converter with 3.5mm jack connector input. {|class=wikitable |- ! Type || ADC Mezzanine || Schematic || Description |- | ...")
- 12:50, 4 October 2012 (diff | hist) m Hardware (→Mezzanine Boards)
- 12:50, 4 October 2012 (diff | hist) N Hardware/Mezzanine/ADC (Created page with "{{TOC right}} == ADC == 8 Channel Analog to Digital Converter with 3.5mm jack connector input. {|class=wikitable |- ! Type || ADC Mezzanine || Schematic || Description |- | ...")
- 12:49, 4 October 2012 (diff | hist) m Hardware
- 14:43, 1 October 2012 (diff | hist) N Components/Libraries/VHDL/SPI (Created page with "{{TOC right}} The toplevel block <code>spiFIFO</code> provides a SPI interface and two FIFO interface. The Slave FIFO interface makes the received data on during a write Tran...") (top)
- 14:40, 1 October 2012 (diff | hist) m Components/Libraries/VHDL/RS232
- 14:36, 1 October 2012 (diff | hist) m Components/Libraries/VHDL
- 14:27, 1 October 2012 (diff | hist) m Standards/Ethernet (→IP cores)
- 14:27, 1 October 2012 (diff | hist) m Standards/Ethernet (→IP cores)
- 14:26, 1 October 2012 (diff | hist) N Components/IP/Ethernet/MII to RAM (Created page with "{{TOC right}} The MII to RAM IP core interfaces the FPGA to a [http://en.wikipedia.org/wiki/Media_Independent_Interface Media Independent Interface (MII)] [http://en.wikipedi...")
- 14:25, 1 October 2012 (diff | hist) m Components/IP/Ethernet
- 14:23, 1 October 2012 (diff | hist) m Components/IP/Ethernet
- 14:23, 1 October 2012 (diff | hist) m Components/IP/SPI
- 14:20, 1 October 2012 (diff | hist) m Components/IP/SPI
- 14:19, 1 October 2012 (diff | hist) N Components/IP/SPI (Created page with "{{TOC right}} SPI Master Slave Architecture The [http://isi.hevs.ch/switzerland/robust-electronics.html ISI] SPI Master IP Core, come...")
- 14:11, 1 October 2012 (diff | hist) N File:SPI master transceiver.png (HDL-Designer Bloc of the SPI Transceiver) (top)
- 14:11, 1 October 2012 (diff | hist) N File:SPI master multi access.png (Simulation of a Multiaccess for the SPI_FIFO bloc) (top)
- 14:10, 1 October 2012 (diff | hist) N File:SPI master FIFO.png (HDL Deisgner Bloc of the SPI_FIFO Master) (top)
- 14:09, 1 October 2012 (diff | hist) N File:SPI timing.png (SPI Timing Diagram) (top)
- 14:09, 1 October 2012 (diff | hist) N File:SPI master slave.png (SPI Master Slave Architecture) (top)
- 13:42, 1 October 2012 (diff | hist) m Components
- 11:17, 1 October 2012 (diff | hist) m Hardware/Stock Programmer
- 11:16, 1 October 2012 (diff | hist) m Hardware/Stock Programmer (→Digilent Xilinx Programmer)
- 11:15, 1 October 2012 (diff | hist) m Hardware/Stock Programmer
- 11:13, 1 October 2012 (diff | hist) N File:Microsemi logo.gif (Logo of Microsemi) (top)
- 11:11, 1 October 2012 (diff | hist) N File:Microsemi fp4 programmer.jpg (Programmer FlashPro 4 from Microsemi (Former Actel)) (top)
- 11:10, 1 October 2012 (diff | hist) m Hardware/Programmers
- 11:08, 1 October 2012 (diff | hist) m Hardware/Programmers
- 11:07, 1 October 2012 (diff | hist) m Hardware/Programmers
- 11:07, 1 October 2012 (diff | hist) m Hardware/Programmers
- 14:33, 26 September 2012 (diff | hist) N User:Hit (Created page with "{{TOC right}} == Office Location == A303 == Contact == * [mailto:thierry.hischier@hevs.ch thierry.hischier@hevs.ch] * [http://isi.hevs.ch/valais/thierry-hischier.html ISI Co...")
- 16:03, 18 September 2012 (diff | hist) m Components/Designs/VHDL template (→Dependencies)
- 16:03, 18 September 2012 (diff | hist) m Components/Designs/VHDL template (→Dependencies)
- 13:42, 14 September 2012 (diff | hist) File:FPGARack v1 0 schematics.pdf (uploaded a new version of "File:FPGARack v1 0 schematics.pdf": Schematic of the FPGA Rack Educational Board v1.0) (top)
- 08:31, 14 September 2012 (diff | hist) File:FPGARack v1 0.ucf (uploaded a new version of "File:FPGARack v1 0.ucf": Pin Contraint File for Board FPGA Rack v1.0.) (top)
- 11:38, 13 September 2012 (diff | hist) N File:FPGA EBS v2 xc3s1200e.ucf (UCF Pin Constrain File for FPGA-EBS Board equipped with the Spartan 3 XC3S1200E Chip) (top)
- 11:38, 13 September 2012 (diff | hist) N File:FPGA EBS v2 xc3s500e.ucf (UCF Pin Constrain File for FPGA-EBS Board equipped with the Spartan 3 XC3S500E Chip) (top)
- 11:37, 13 September 2012 (diff | hist) m Hardware/FPGAEBS (→Board families)
- 11:37, 13 September 2012 (diff | hist) m Hardware/FPGAEBS
(Latest | Earliest) View (newer 50 | older 50) (20 | 50 | 100 | 250 | 500)