Search results
Create the page "SPI" on this wiki!
Page title matches
File:SPI master slave.png SPI Master Slave Architecture(500 × 200 (8,838 bytes)) - 12:09, 1 October 2012File:SPI timing.png SPI Timing Diagram(500 × 291 (48,238 bytes)) - 12:09, 1 October 2012File:SPI master FIFO.png (541 × 588 (12,890 bytes)) - 12:10, 1 October 2012File:SPI master multi access.png (1,121 × 388 (15,027 bytes)) - 12:11, 1 October 2012File:SPI master transceiver.png HDL-Designer Bloc of the SPI Transceiver(430 × 499 (8,062 bytes)) - 12:11, 1 October 2012- [[File:SPI_master_slave.png|200px|SPI Master Slave Architecture]] ...sted. The SPI bloc can also be found in the template design in the library SPI.2 KB (306 words) - 12:53, 24 January 2013
- The toplevel block <code>spiFIFO</code> provides a SPI interface and two FIFO interface. The Master FIFO interface serves as buffer for data to send on the SPI line.935 B (130 words) - 12:43, 1 October 2012
Page text matches
- ...anSat/Master_FPGA CanSat Master FPGA] - ''Spartan 6 XC6SLX9 and 8Mb M25P80 SPI PROM''6 KB (745 words) - 09:23, 6 September 2022
- * [[Components/IP/SPI|SPI IP Core]]1 KB (169 words) - 12:34, 6 June 2018
- ├───SPI -- Library SPI for SPI Communication └───SPI_test -- Testbench for Library SPI10 KB (1,006 words) - 07:12, 10 June 2016
- ## Choose No for Attaching SPI or BPI PROM # Right Click on the Blue SPI/BPI Symbol4 KB (567 words) - 06:49, 15 July 2014
- ; [[Components/Libraries/VHDL/SPI|SPI]] : SPI Communication2 KB (218 words) - 15:06, 2 August 2018
- ...VHDL|up_name=VHDL libraries|right=Components/Libraries/VHDL/SPI|right_name=SPI}}994 B (134 words) - 08:55, 3 December 2012
File:SPI master slave.png SPI Master Slave Architecture(500 × 200 (8,838 bytes)) - 12:09, 1 October 2012File:SPI timing.png SPI Timing Diagram(500 × 291 (48,238 bytes)) - 12:09, 1 October 2012File:SPI master transceiver.png HDL-Designer Bloc of the SPI Transceiver(430 × 499 (8,062 bytes)) - 12:11, 1 October 2012- [[File:SPI_master_slave.png|200px|SPI Master Slave Architecture]] ...sted. The SPI bloc can also be found in the template design in the library SPI.2 KB (306 words) - 12:53, 24 January 2013
- The toplevel block <code>spiFIFO</code> provides a SPI interface and two FIFO interface. The Master FIFO interface serves as buffer for data to send on the SPI line.935 B (130 words) - 12:43, 1 October 2012
- == CSR USB to SPI Converter == [[File:csr-usb-spi.jpg]]2 KB (293 words) - 11:48, 10 September 2014
- * Some serial buses (UART, SPI, I2C) | style="background:#ffffff ; text-align:left" | SPI-Bus clock signal17 KB (2,529 words) - 14:32, 5 April 2017
- * Two RJ45 connectors for EtherCAT port connection through soft SPI core in the fabric and external PHY) * SPI headers2 KB (333 words) - 13:07, 27 February 2013
- ...d Low Energy sniffer, with concurrent capture of spectrum, HCI (USB, UART, SPI), WCI-2, logic signals, and Audio I2S. See http://www.ellisys.com/products/2 KB (218 words) - 06:50, 16 September 2015
- | Gyroscope || ST L3GD20 || i2c/SPI MEMS 3-axis digital gyroscope || U23 || [[Media:L3GD20.pdf|datasheet]]3 KB (424 words) - 09:39, 13 May 2016
- ## Choose No for Attaching SPI or BPI PROM # Right Click on the Blue SPI/BPI Symbol4 KB (565 words) - 13:01, 20 January 2015
- * baudRateDivide, which gives the SPI clock rate as a function of the system clock The [[Hardware/Parallelport/heb_lcd|display's]] maximal SPI rate is 20 MHz.11 KB (1,130 words) - 14:24, 16 January 2018
- * automatically on boot via the onboard FLASH memory (SPI x1/x4). * '''OK''' FPGA boot FLASH programming/booting (with SPI 1x and 4x).5 KB (779 words) - 10:42, 12 December 2016
- ...le using a common abstraction layer. Common functions are provided for the SPI, UART and I2C buses. Peripherals used : SPI, leds10 KB (1,486 words) - 08:06, 21 April 2016